In general, a static random access memory (SRAM) tends to have aggressive design rules to reduce the size of devices and increase the capacity in the system on chip (SoC) solutions. Therefore, the SRAM is more susceptible to process variability. Also, while the operation voltage is being scaled with the reduction in the size of devices, the threshold voltage of the transistor is not scaling at the same rate, which means that chip designers have less voltage headroom for the transistors.
The voltage scaling with the reduction in the size of devices, i.e., the above reduction in voltage headroom, is limited by static noise margin (SNM). SNM is an important SRAM parameter that is a direct measure of how well an SRAM memory cell can maintain a logic state “0” or “1” when the SRAM memory cell is perturbed by noise or with intrinsic imbalance between the cross-coupled inverters and leakage defects within the transistors forming the SRAM bit. An SRAM bit can easily be upset when accessed if the SRAM is designed with insufficient SNM throughout its operating voltage range. The SRAM bit is accessed when the word line for the bit is activated (e.g. high) for either reading from that bit, or for writing to another bit on the same row of the memory array but on a different column of that memory array. When a lower supply voltage (e.g., Vdd) is used and the bit line precharges to Vdd, the SRAM circuit has a minimum power supply voltage limitation because of SNM.
A dual rail SRAM is used to avoid the SNM limitation at lower voltage. The dual rail SRAM feature is also associated with dynamic power reduction techniques. In one such technique, a part of the memory, called a memory periphery logic circuit, operates at a lower power supply voltage Vdd than the SRAM-bit in order to reduce dynamic power consumption. This technique allows for reduction of the active power while maintaining sufficient performance. For example, the bit cell can use another power supply voltage, e.g. CVdd, where CVdd is usually higher than Vdd, in order to maintain a sufficient SNM.
However, when the above technique is used a PMOS transistor in a dual rail SRAM circuit that is supposed to be turned off may have a gate voltage lower than a power supply voltage supplied to the source of the PMOS transistor because of circuit connections to different power supply voltages, e.g. Vdd and CVdd. Therefore, this PMOS transistor does not fully turn off. Because the PMOS transistor is not properly turned off, current leaks through a direct current path between the power supply and ground during read/write operations or while the SRAM is in standby mode. Accordingly, new methods for dual rail SRAM are desired.